Flip-Chip Technologies and Global Markets - a new market research report on companiesandmarkets.com
PR-Inside.com: 2014-04-29 05:09:02
The global market for Flip Chip Technology by wafer bumping process reached $18.9 billion in 2012. This market is expected to grow to $20.1 billion in 2013 and $36.5 billion in 2018, a compound annual growth rate (CAGR) of 12.7% over the five-year period from 2013 to 2018.
Cu pillar process, as a segment is expected to reach $7.3 billion in 2013. It is further expected to grow to nearly $24.9 billion in 2018, a CAGR of 27.6% over the five-year period from 2013 to 2018.
Gold stud bumping process, as a segment is expected to reach $5.5 billion in 2013. It is further expected to grow to $6.0 billion in 2018, a CAGR of 1.6% over the five-year period from 2013 to 2018.
The global market for flip chip technology was valued at $18.9 billion in 2012 and is expected to increase to $20.1 billion in 2013. BCC Research projects the market to grow to nearly $36.5 billion by 2018, and register a five-year compound annual growth rate of 12.7% from 2013 to 2018.
Flip chip technology has enabled electronics technology to reach new levels of performance, while fueling the growth of global markets for semiconductors, electronic devices and a host of industrial and consumer products. In recent years, the growth of flip chip interconnect technology over other interconnect technologies has been remarkable because of the increasing complexity of the architecture of chip design and fabrication.
Flip chip technology is used to interconnect semiconductor devices, such as integrated circuits (ICs), to external circuitry by means of solder bumps that have been deposited onto chip pads. Traditionally, semiconductor devices use wire bonds to connect devices from substrates or other active components. Due to the shrinking size of chips and demand for more sophisticated structures, demand for flip chips with controlled collapse chip connection (C4) technology has grown significantly. Features such as improved thermal heat transfer and improved performance at higher frequencies have also driven the market for flip chips.
Various wafer bumping technologies, such as tin-lead (Sn-Pb) and gold stud bumping, are used extensively in flip chip bumping and account for the major share of the market. However, government regulations and the high cost of the materials used in these processes are expected to result in them being replaced by copper (Cu) pillar bumping, as it is a high-performance, low-cost, and nontoxic process. In terms of applications of Cu pillar bumping, communication devices and other computing devices are expected to drive the market in the near term.
Severe warpage of a substrate after the flip chip assembly process may lead to fracture of solder joints, underfill delamination or underfill cracks, decreasing the lifespan of chips. Recent work has shown that the unstable contact resistance of electrically conductive adhesives on copper and tin is due to electrochemical corrosion of these metals under elevated temperature and humidity conditions.
Technological advancements include a new class of conductive adhesives that exhibit exceptional contact resistance stability on surfaces including organic solderability preservative (OSP) copper, Sn alloys and even 100% Sn. Advancements such as this have reduced lead times. Demand for flip chips in applications such as the CMOS 28 nm IC and new applications such as application processor engines, base band modules, double data rate memory and the 3DIC/2.5D interposer, using micro bumping, is expected to increase in the near future.
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